ISSN (Online) : 2456 - 0774

Email : ijasret@gmail.com

ISSN (Online) 2456 - 0774

FPGA IMPLEMENTATION OF AN IMPROVEDWATCHDOG TIMER FOR SAFETY-CRITICALAPPLICATIONS 

Abstract

Abstract: Embedded systems that are employed in safety critical applications require highest reliability. External watchdogtimers are used in such systems to automatically handle and recover from operation time related failures. Most of the availableexternal watchdog timers use additional circuitry to adjust their timeout periods and provide only limited features in termsof their functionality. This project describes the architecture and design of an improved configurable watchdog timer that canbe employed in safety-critical applications. Several fault detection mechanisms are built into the watchdog, which adds to itsrobustness. The functionality and operations are rather general and it can be used to monitor the operations of any processorbased real-time system. This project also discusses the implementation of the proposed watchdog timer in a FieldProgrammable Gate Array (FPGA). This allows the design to be easily adaptable to different applications, while reducing theoverall system cost. The effectiveness of the proposed watchdog timer to detect and respond to faults is first studied byanalyzing the simulation results. The design is validated in a real-time hardware by injecting faults through the software whilethe processor is executing, and conclusions are drawn.

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Paper Submission Open For April  20212
UGC indexed in (Old UGC) 2017
Last date for paper submission 30th April, 2022
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Publication of Paper Within 01-02 Days after completing all the formalities
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